Design Verification Engineer

About the role

The Design Verification Engineer will be responsible for the verification of complex IPs or SoCs. The role involves utilizing C and SystemVerilog/UVM to ensure design integrity and performance.

Responsibilities

• Verify complex IPs or SoCs using C and SystemVerilog/UVM
• Develop and execute test plans
• Implement verification technologies including code coverage, functional coverage, and assertions
• Work with AMBA protocols such as AXI, AHB, and APB
• Collaborate on projects involving ARM processors

Required skills

• Verilog
• SystemVerilog
• UVM
• DDR SDRAM
• AXI
• Test Planning
• ARM architecture
• C
• AMBA protocols
• AHB
• APB
• Code Coverage
• Functional Coverage
• Assertions

Nice to have

• USB
• DDR
• PCIE
• Ethernet
• MIPI
• OVM