Senior FPGA Developer

About the role

The Senior FPGA Developer will be a member of the core team building the Quantum Key Distribution system. The role involves end-to-end RTL ownership on AMD/Xilinx platforms, including architecture, implementation, verification, and timing closure for high-rate interfaces and deterministic pipelines. The developer will also set engineering standards and mentor junior staff.

Responsibilities

• Owning SystemVerilog RTL architecture and implementation for Artix-7 and Kintex UltraScale.
• Integrating DDR3/DDR4 controllers, PCIe endpoints, and Ethernet/SFP paths.
• Building deterministic acquisition, timing, and sifting layers including packetization and buffering.
• Defining AXI/AXI-Stream boundaries and register maps for software integration.
• Authoring XDC constraints and achieving consistent timing closure across corners.
• Applying floorplanning and CDC methodology to ensure design margin.
• Establishing verification environments using ModelSim/Questa and integrating Python/cocotb.
• Managing board bring-up, debug, and bitstream release processes.

Required skills

• SystemVerilog
• RTL
• AMD/Xilinx
• Vivado
• DDR3/DDR4
• PCIe
• Ethernet
• XDC
• CDC
• ModelSim
• Questa
• Python
• cocotb
• AXI

Nice to have

• OSVVM
• UVM